Generally, so-called power gating has been known as a technology that reduces the power consumption of a large scale integration circuit (LSI), i.e., a technology for cutting off the source voltage supplied to circuits inside a semiconductor chip (internal circuits) and placing the internal circuits into what is known as a sleep state. The techniques related to power gating include one that prevents an internal state or internal data from being erased upon cutoff of the source voltage. For example, PTL 1 describes a technique by which a volatile register and a nonvolatile register are provided. According to this technique, data is saved from the volatile register to the nonvolatile register when the supply of the source voltage is cut off, and the data is restored from the nonvolatile register to the volatile register when the supply of the source voltage is resumed.
For example, PTL 2 describes a nonvolatile flip-flop circuit that uses magnetic tunnel junction (MTJ) elements making up a nonvolatile storing section for storing the internal state and internal data when the supply of the source voltage is cut off.
FIG. 11 depicts a typical circuit diagram of an existing nonvolatile flip-flop circuit that uses MTJ elements constituting a nonvolatile storing section. A nonvolatile flip-flop circuit 1016 depicted in FIG. 11 includes a master latch 1030, a slave latch 1032, positive metal-oxide semiconductor (PMOS) transistors P5 and P6, and MTJ elements MTJ1 and MTJ2. The master latch 1030 includes inverters IV1 and IV2, a Not-And (NAND) circuit NAND1, and transfer gates TG1 to TG3. Further, the slave latch 1032 includes inverters IV5 and IV6, a PMOS transistor P7, a NAND circuit NAND2, and a transfer gate TG4. The transfer gates TG1 to TG4 are controlled by a clock signal CB obtained by an inverter IV10 inverting a clock signal CLK and by a clock signal C (with the same logical value as that of the clock signal CLK) acquired by an inverter IV11 inverting the output of the inverter IV10.
In the existing nonvolatile flip-flop circuit 1016 depicted in FIG. 11, if the supply of the source voltage is to be cut off by power gating, the logical value of a control signal SR is set to “0” to turn on the PMOS transistors P5 to P7 whose gate is impressed with the control signal SR. Then logical values “1” and “0” of a control signal CTRL are fed consecutively, thereby writing one-bit information held in the slave latch 1032 to the MTJ elements MTJ1 and MTJ2. At the end of power gating, the supply of the source voltage is resumed, and the logical value of the control signal SR is set to “0” to turn on the PMOS transistors P5 to P7. This permits restoration into the slave latch 1032 of the internal circuit state applicable when the above-described write operation was performed, through the use of a difference in resistance value between the MTJ elements MTJ1 and MTJ2.